1. Field of the Invention
The present invention relates to a technology for transferring data from a memory of a transmitting side to a memory of a receiving side, with an improvement of a speed of data transfer and a decrease in a load to operation processing units of the transmitting side and the receiving side by eliminating an exchange of transmitting and receiving addresses.
2. Description of the Related Art
In a disk array apparatus, it is necessary to transfer control information and the like between a channel adapter (CA) that operates as an interface with a host, and a cache manager (CM) that manages a cache.
FIG. 8 is a schematic for illustrating a structure of a conventional disk array apparatus. A disk array apparatus 7 is connected to a host 2 via a fiber channel link 3, having a CA 70, a plurality of CMs 80, and a disk 90. The CA 70 and the CMs 80 are connected via a peripheral component interconnect (PCI) bus, and several bridges and switches intervene between the CA 70 and the CMs 80.
The CA 70 has a CA-MPU 71 serving as an operation processing unit, a corresponding CA memory 72, and a large-scale integrated-circuit (LSI) 700 that includes a direct-memory-access (DMA) engine for transferring data between the CA 70 and the CMs 80. The CM 80 includes a cache manager-micro processing unit (CM-MPU) 81 serving as an operation processing unit and a corresponding CM memory 82. Data transfer of 8 bytes to 512 bytes of control information is performed between the CA 70 and the CMs 80 before the DMA transfer and the like.
FIG. 9 is a schematic for explaining a conventional sequence of data transfer from the CM 80 to the CA 70 (a read sequence). In the data transfer from the CM 80 to the CM 70, the CM-MPU 81 stores a message (MSG), which is data to be transferred to the CM memory 82, and a memory address (ADR) in which the message is stored. The LSI 700 occasionally reads that the CM 80 is in a transferable state and confirms the state (*).
If the CM 80 is in the transferable state, the CM-MPU 81 stores (writes) the address (ADR), in which the transfer message (MSG) is stored, in the CA memory 72 ((1)). Then, the CM MPU 81 writes an address (WP) of the CA memory 72, in which the ADR is stored, in the LSI 700. The LSI 700 notifies the CA-MPU 71 of the presence of the WP ((2) broken line).
According to the notification from the LSI 700, the CA-MPU 71 reads an interrupt factor to detect the presence of the WP in the LSI 700 and reads the WP on the LSI 700 to read the ADR, in which the message is stored, from the CA memory 72 designated by the WP ((3)).
The CA-MPU 71 notifies the LSI 700 of the ADR information to start the LSI 700 ((4)). The started LSI 700 transfers the message on the CM memory 82 designated by the ADR to the CA memory 72 ((5)).
FIG. 10 is a schematic for explaining a conventional sequence of data transfer from the CA 70 to the CM 80 (a write sequence). As shown in the figure, in data transfer from the CA 70 to the CM 80, the CA-MPU 71 uses a DMA function of the LSI 700 to write a message (MSG) in the CM memory 82 ((1)).
The CA-MPU 71 writes an address, in which the message is stored, on a register of the LSI 700 ((2)). The LSI 700 notifies the CM-MPU 81 of the presence of the address by generating an interrupt ((3)). Then, the CM-MPU 81 having received the interrupt reads an interrupt factor and the address ((4)). Then, the CM-MPU 81 notifies the LSI 700 of the address of the processed message ((5)).
Regarding a message transfer between processors, for example, Japanese Patent Application Laid-Open No. H3-174645 discloses a technique for transferring a message between CPUs using a shared random access memory (RAM).
In the read sequence shown in FIG. 9, the CM-MPU 81 determines an address of the CM memory 82 in which the transmission message is stored. Thus, the CM-MPU 81 is required to notify the CA-MPU 71 of this address before the DMA is started. In addition, in the write sequence shown in FIG. 10, since the CA-MPU 71 determines a transmission destination address, it is unnecessary to perform communication between MPUs before the DMA is started. However, the CA-MPU 71 is required to notify the CM-MPU 81 of the transmission destination address after the DMA is started.
It is necessary to communicate address information between the MPUs in both the sequences. In the communication between the MPUs, the CA 70 and the CMs 80 are connected by a PCI bus or a switch. Thus, a communication takes long time and a large load is imposed on the MPUs.
Another problem in a message transfer between the CPUs described in Japanese Patent Application Laid-Open No. H3-174645 is that a shared RAM is required.